DRAM Design Validation Engineer

Responsibilities

could include: Working with design, verification and integration engineers to ensure memory controller requirements are well defined and cover the scope of DRAM based corner cases Collaborating with Architecture and DRAM vendors for Apple’s main memory solution Ensuring DRAM simulation Ensuring the internal and external DRAM silicon and package level testing Drive the validation and qualification of DRAM with memory vendors Debugging RMA material with apparent DRAM related defects Collaborating with the DRAM vendors to improve test coverage Drive roadmaps and specs of memory vendors for next technology node devices Master's Degree in Electrical Engineering, Computer Engineering or Computer Science Expert in DRAM cell architectures Expert of DRAM memory organization and periphery design for low DRAM power Expertise in DRAM simulation Experience in memory interface verification with understanding DDR-PHY and Memory Controller Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5) characterization and qualification Understanding of memory test patterns Knowledge of DRAM reliability Knowledge with innovative packaging technology (POP, TSV, etc.) and their relationship to DRAM signal/power integrity Previous experience in Failure Analysis of DRAM devices Excellent hardware and software debug skill Experience working with the major DRAM vendors Strong background in computer architecture Programming experience in C/C++