Junior DV and FPGA Prototyping Engineer

Your on-job tasks would consist of

- Studying AMD Vivado and Vitis IDE

- Modelling (Python) and RTL implementation (System Verilog) of the proposed image and/or audio processing algorithms

- Building FPGA environment and debug of the implemented RTL design using Zybo Z7 board

- Building SV based verification environment for simple RTL designs like FIFO, UART.

We’d expect you to learn:

o OOP concepts in System Verilog (classes, inheritance, polymorphism)

o Constrained randomization (rand variables, constraints, inline constraints, conflict solving)

o Functional coverage (covergroups, coverpoints, cross coverage, bins)

o Assertions (simple SVA properties checks)

- Studying UVM methodology

- Wrapping SV based environment into UVM

- Shell and Python scripting

Mandatory qualifications

- Bachelor’s/Master’s Degree in Electronics or related fields

- Good understanding of digital logic design basics

- Basics of IC design & verification using System Verilog

- Beginner’s experience with EDA tools (AMD Vivado (Xilinx), Intel Quartus (Altera), Cadence, Synopsys or similar)

- Understanding OOP concepts

- Beginner’s level of English or higher

Optional qualifications you may have

- FPGA design using HDL (Verilog, VHDL) or schematics editor

- CPU architecture knowledge, embedded SW development

- Scripting using Bash, Python, TCL etc.