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Sr. SOC RTL integration

NXP Semiconductors Shanghai (Pudong), China
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Experience
Not specified
Qualification
Review official listing
Posted
10 Oct 2026
Closing date
Check source
Salary
Not disclosed

Job information

About this opportunity

Employer: NXP Semiconductors | Original listing

Quick summary

NXP Semiconductors Shanghai (Pudong), China Architecture Not specified

Responsibilities

  • Lead subsystem and SoC-level RTL integration for complex SoC products from architecture definition through tape-out.
  • Own and maintain SOC RTL integration, including IP assembly, connectivity, configuration, and design quality checks.
  • Define and implement SoC interconnect, clocking, reset, and power architectures to meet performance, power, and functional requirements.
  • Collaborate closely with architects to translate architectural specifications into robust RTL implementations.
  • Work with IP, Verification, DFT and Physical Design teams to resolve integration challenges and drive project milestones.
  • Drive continuous improvement of SoC integration methodologies, automation flows, and design quality.

Requirements

  • 5+ years (Senior level) of ASIC/SoC design and integration experience.
  • Strong Verilog coding skills with solid understanding of digital logic design
  • Deep understanding of AMBA (AXI/AHB/APB) protocols and NoC/NIC based architectures
  • Strong knowledge of low power design methodologies
  • Experience with industry-standard EDA tools for lint, CDC, RDC, and low-power verification
  • Knowledge of automotive/industrial functional safety is a strong plus.
  • Excellent communication and cross-functional collaboration skills.


More information about NXP in Greater China...

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Listing details

Employer
NXP Semiconductors
Location
Shanghai (Pudong), China
Structured address
Shanghai (Pudong)
Category
Architecture
Base salary
Not disclosed
Valid through
Check official source
Reference
R-10065807
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